But if you use (v-1) elsewhere in your code, the tools will or may reuse it, thus making the overall thing actually take up less space than some other alternatives. The 'minus one' operation here is kinda 'expensive'. Unless you're going to instantiate myriads of such detectors, a few LUTs of difference won't make the slightest difference!) One concrete thing to note, is also that the end result in a given design will depend on a lot of factors.

The above 'modulo' method is actually one of the fastest (at least for non-pipelined approaches) once synthesized (not the fastest, but pretty good), is simple to understand and simple to read from code, yields pretty compact code (which is always a plus for maintenance and validation), is provably correct, and takes up reasonable area (sure it's not the least area-hungry, but it's still reasonable. And good engineering is actually all about finding the simplest solution that meets ALL requirements of a given problem. Don't leave such circuitry to the would create a glitchy hairball. Note that, if your FPGA has a different LUT construction ( like 8 input, 4 output or 4 input 3 output ) then other optimisations are possible. There are not race conditions as all signals have passed the same amount of LUT's. signals passing a column all exet with the same propagation delay.

since MTO is high the output will be low. in the last column both ALO and MTO goes high. in the second column we get both ALO's high and nothing registers on MTO's. in the first column we get ALO from Lut1 high, andnd ALO from LUT3 high, nothing registers on the MTO's. Example : lets try a number where A0 if high and A5 is high. Simply tell the synthesizer it needs to implement this as-is and not minimize the logic. If one MTO is high the output will be low. All MTO signals propagate through the OR-tree. MTO : there is more than one high (and gate ) ,we feed those into an or-tree. ALO : there is at least one input high ( OR gate ), we will re-evaluate that in the next block. The idea is based on thinking 'in reverse'. you only need a NAND gate as output then. You can combine the three input or and the inverter also into one lut. Since a LUT typically has 4 inputs and 2 outputs you can combine two OR gates into one lut. Note that the last step ( two inverters and an OR gate ) could have been done differently but it would have unbalanced the propagation delay creating very glitchy output. This guarantees a known fixed propagation delay ( the actual gates are LUT's which have a constant propagation time irrespective of the type of gate created ).

Verilog bit count